2K Dual Input PiP De-interlacer/Scaler/Warping/Edge-blending LSI

The IP00C812B is a dual-input/dual-output de-interlacer and scaler on a single device.

It features a built-in video decoder, ARM9 CPU, LVDS output, along with Ethernet and USB interfaces.

Its inputs and outputs can be any interlaced format, SD or HD, or any progressive format, up to 1080P/WUXGA/2K1K.

The IP00C812B features 2 independent de-interlacer/scaler blocks, with full 10-bit internal processing.

The IP00C812B can be configured in several ways.

In the single-output mode, it can generate Picture-in-Picture, Picture-by-Picture output.

In the dual-output mode, it can generate separate outputs at any resolution, or it can serve to drive directly a 3-D display, using its quad-LVDS output port.

The IP00C812B has a state-of-the-art image processing algorithms, such as mirror image, 90-degree rotation, keystone correction and color uniformity control.

It is energy-efficient, with its separate power blocks for CPU and image processing, thus greatly reducing stand-by power consumption.

The IP00C812B is an ideal solution to drive a 3-D display, with no other components required, other than the front-end image signal receiver.

The IP00C812B is a cost-effective way to eliminate FPGA resources by handling the common image processing tasks of 2 video channels on the board.

The advantages of the IP00C812B are reduced board space, ease of programming, and cost.





Video Decoder

PiP & PoP Functions

Bitmap OSD

Embedded CPU


External CPU Interface

Image Quality Control

External Memory

Power Supply


IP00C812B Example Application IP00C812B Block Diagram