The IP00C812B is a dual-input/dual-output de-interlacer and scaler on a single device.

It features a built-in video decoder, ARM9 CPU, LVDS output, along with Ethernet and USB interfaces.

Its inputs and outputs can be any interlaced format, SD or HD, or any progressive format, up to 1080P/WUXGA/2K1K.

The IP00C812B features 2 independent de-interlacer/scaler blocks, with full 10-bit internal processing.

The IP00C812B can be configured in several ways.

In the single-output mode, it can generate Picture-in-Picture, Picture-by-Picture output.

In the dual-output mode, it can generate separate outputs at any resolution, or it can serve to drive directly a 3-D display, using its quad-LVDS output port.

The IP00C812B has a state-of-the-art image processing algorithms, such as mirror image, 90-degree rotation, keystone correction and color uniformity control.

It is energy-efficient, with its separate power blocks for CPU and image processing, thus greatly reducing stand-by power consumption.

The IP00C812B is an ideal solution to drive a 3-D display, with no other components required, other than the front-end image signal receiver.

The IP00C812B is a cost-effective way to eliminate FPGA resources by handling the common image processing tasks of 2 video channels on the board.

The advantages of the IP00C812B are reduced board space, ease of programming, and cost.

Input

• 30-bit RGB/30-bit YUV4:4:4/20-bit YUV4:2:2/10-bit YUV4:2:2@166MHz

• 60-bit RGB/60-bit YUV4:4:4/40-bit YUV4:2:2@83MHz(Parallel)

• Analog: CVBS/S-Video

• 2176 pixels of active video

Output

• 2 dual-LVDS outputs@135MHz each

• Formats:30-bit RGB/YUV4:4:4 or 20-bit YUV4:2:2@166MHz

• 2176 pixels of active video

• Pixel clock synchronization for driving 4K output

De-Interlacing

• Motion adaptive de-interlacer

• Diagonal line interpolation

• 3D/MPEG/mosquito/block noise reduction

• 2:2, 2:3 and multi cadence detection

• Chroma bug canceller

Scaling

• 6symbol filter (horizontal only-8symbol) with FIR filter

• Independent H and V scaling ratios (aspect ratio correction)

• Coefficient filter ROM embedded (64set)

• 90degree image rotation

• Vertical keystone correction

• H and V flip circuits for image and OSD

Video Decoder

• NTSC-M, JPN, 4.43 PAL-B, D, G, H, I, CombinationN, 60, &SECAM

• VBI(Closed caption/CGMS/WSS)data extraction

• Clamp Pulse output

• Dot interference, cross color removal

PiP & PoP Functions

• Two(2) fully independent video inputs

• Frame rate conversion with frame tear protection

Bitmap OSD

• 256colors/High color OSD (RGB565)compatible

• Embedded font engine(65536words)

• Support for blinking and semi-transparent(4color)OSD

Embedded CPU

• ARM926EJ-S core with 16KB instruction, 8KB data

• Work RAM(64KB)

• Ethernet, USB2.0(host, function)

• DMAC(2ch)/UART(4ch)/I2C(master/slave)

• Timer(4ch)/Interruption control/IR remote control/RTC

• 10-bit ADC(8ch)/10-bit DAC(6ch)

3D

• HDMI 1.4a compatible (with external receiver & transmitter)

• 120MHz alternate output, 60Hz simultaneous output

External CPU Interface

• 8-bit parallel, 4-line serial(with external CPU)

• External connection to Flash/SRAM/SDRAM

• Address:25-bit/Data:16-bit

• External interruption input(4 line)

Image Quality Control

• 12-bit gamma correction with interpolation (up to 7 LUTs available)

• Bias x3, Gain x2, CSC equipped for RGB <-> YUV

• Color management function

• Fully compatible with xvYCC

• Uniformity correction

• Input image detection of APL, Histogram, Min/Max, edge strength/position measurement, etc.

External Memory

• Memory-bus 64-bit 800MHz

• DDR3-SDRAM PC800(1G/512M/bit x16)x4

Power Supply

• 3.3V, 1.5V and 1.2V

• Separate power consumption (Scaler and CPU)

Package

• 900-pin BGA, 35mmx35mm (1mm pitch)